Pentium II and III Xeon

• PII Xeon
  • Variants
    • 400 MHz Introduced June 29, 1998
    • 450 MHz (512 KB L2 Cache) Introduced October 6, 1998
    • 450 MHz (1 MB and 2 MB L2 Cache) Introduced January 5, 1999
• PIII Xeon
  • Introduced October 25, 1999
  • Number of transistors: 9.5 million at 0.25 µm or 28 million at 0.18 µm
  • L2 cache is 256 KB, 1 MB, or 2 MB Advanced Transfer Cache (Integrated)
  • Processor Package Style is Single Edge Contact Cartridge (S.E.C.C.2) or SC330
  • System Bus clock rate 133 MHz (256 KB L2 cache) or 100 MHz (1–2 MB L2 cache)
  • System Bus Width 64 bits
  • Addressable memory 64 GB
  • Used in two-way servers and workstations (256 KB L2) or 4- and 8-way servers (1–2 MB L2)
  • Family 6 model 10
  • Variants
    • 500 MHz (0.25 µm process) Introduced March 17, 1999
    • 550 MHz (0.25 µm process) Introduced August 23, 1999
    • 600 MHz (0.18 µm process, 256 KB L2 cache) Introduced October 25, 1999
    • 667 MHz (0.18 µm process, 256 KB L2 cache) Introduced October 25, 1999
    • 733 MHz (0.18 µm process, 256 KB L2 cache) Introduced October 25, 1999
    • 800 MHz (0.18 µm process, 256 KB L2 cache) Introduced January 12, 2000
    • 866 MHz (0.18 µm process, 256 KB L2 cache) Introduced April 10, 2000
    • 933 MHz (0.18 µm process, 256 KB L2 cache)
    • 1000 MHz (0.18 µm process, 256 KB L2 cache) Introduced August 22, 2000
    • 700 MHz (0.18 µm process, 1–2 MB L2 cache) Introduced May 22, 2000

Celeron (Pentium III Coppermine-based)

• Coppermine-128, 0.18 µm process technology
  • Introduced March, 2000
  • Streaming SIMD Extensions (SSE)
  • Socket 370, FC-PGA processor package
  • Number of transistors: 28.1 million
  • 66 MHz system bus clock rate, 100 MHz system bus clock rate from January 3, 2001
  • 32 kB L1 cache
  • 128 kB Advanced Transfer L2 cache
  • Family 6 model 8
  • Variants
    • 533 MHz
    • 566 MHz
    • 600 MHz
    • 633, 667, 700 MHz Introduced June 26, 2000
    • 733, 766 MHz Introduced November 13, 2000
    • 800 MHz Introduced January 3, 2001
    • 850 MHz Introduced April 9, 2001
    • 900 MHz Introduced July 2, 2001
    • 950, 1000, 1100 MHz Introduced August 31, 2001
    • 550 MHz (Mobile)
    • 600, 650 MHz (Mobile) Introduced June 19, 2000
    • 700 MHz (Mobile) Introduced September 25, 2000
    • 750 MHz (Mobile) Introduced March 19, 2001
    • 800 MHz (Mobile)
    • 850 MHz (Mobile) Introduced July 2, 2001
    • 600 MHz (LV Mobile)
    • 500 MHz (ULV Mobile) Introduced January 30, 2001
    • 600 MHz (ULV Mobile)

XScale (chronological entry)

• Introduced August 23, 2000

Pentium 4 (not 4EE, 4E, 4F), Itanium, P4-based Xeon, Itanium 2 (chronological entries)

• Introduced April 2000 – July 2002
• See main entries

Celeron (Pentium III Tualatin-based)

• Tualatin Celeron – 0.13 µm process technology
  • 32 KB L1 cache
  • 256 KB Advanced Transfer L2 cache
  • 100 MHz system bus clock rate
  • Socket 370
  • Family 6 model 11
  • Variants
    • 1.0 GHz
    • 1.1 GHz
    • 1.2 GHz
    • 1.3 GHz
    • 1.4 GHz

Pentium M

At the end of the 1990s, Intel launched two of its best-known processor brands: Celeron and Xeon. The former was aimed at the budget market and the latter at servers, and sometimes workstations. The first Celeron (Covington) was a Pentium II without a Level 2 cache, and suffered extremely poor performance, whereas the Pentium II Xeon had a large cache. Even now, both brands still exist—Celeron for the entry-level market (generally with a reduced cache and a slower FSB) and Xeon for servers (with a fast FSB, sometimes more cache, and high clockspeeds).

Intel quickly added a cache to the Celeron with the Mendocino model (128 KB). The Celeron 300A is famous for its overclocking capacities, able to go 50% or more above its rated clock speed much of the time.

• Banias 0.13 µm process technology
  • Introduced March 2003
  • 64 KB L1 cache
  • 1 MB L2 cache (integrated)
  • Based on Pentium III core, with SSE2 SIMD instructions and deeper pipeline
  • Number of transistors 77 million
  • Micro-FCPGA, Micro-FCBGA processor package
  • Heart of the Intel mobile Centrino system
  • 400 MHz Netburst-style system bus
  • Family 6 model 9
  • Variants
    • 900 MHz (ultra low voltage)
    • 1.0 GHz (ultra low voltage)
    • 1.1 GHz (low voltage)
    • 1.2 GHz (low voltage)
    • 1.3 GHz
    • 1.4 GHz
    • 1.5 GHz
    • 1.6 GHz
    • 1.7 GHz
• Dothan 0.09 µm (90 nm) process technology
  • Introduced May 2004
  • 2 MB L2 cache
  • 140 million transistors
  • Revised data prefetch unit
  • 400 MHz Netburst-style system bus
  • 21W TDP
  • Family 6 model 13
  • Variants
    • 1.00 GHz (Pentium M 723) (ultra low voltage, 5W TDP)
    • 1.10 GHz (Pentium M 733) (ultra low voltage, 5W TDP)
    • 1.20 GHz (Pentium M 753) (ultra low voltage, 5W TDP)
    • 1.30 GHz (Pentium M 718) (low voltage, 10W TDP)
    • 1.40 GHz (Pentium M 738) (low voltage, 10W TDP)
    • 1.50 GHz (Pentium M 758) (low voltage, 10W TDP)
    • 1.60 GHz (Pentium M 778) (low voltage, 10W TDP)
    • 1.40 GHz (Pentium M 710)
    • 1.50 GHz (Pentium M 715)
    • 1.60 GHz (Pentium M 725)
    • 1.70 GHz (Pentium M 735)
    • 1.80 GHz (Pentium M 745)
    • 2.00 GHz (Pentium M 755)
    • 2.10 GHz (Pentium M 765)
• Dothan 533 0.09 µm (90 nm) process technology
  • Introduced Q1 2005
  • Same as Dothan except with a 533 MHz NetBurst-style system bus and 27W TDP
  • Variants
    • 1.60 GHz (Pentium M 730)
    • 1.73 GHz (Pentium M 740)
    • 1.86 GHz (Pentium M 750)
    • 2.00 GHz (Pentium M 760)
    • 2.13 GHz (Pentium M 770)
    • 2.26 GHz (Pentium M 780)
• Stealey 0.09 µm (90 nm) process technology
  • Introduced Q2 2007
  • 512 KB L2, 3W TDP
  • Variants
    • 600 MHz (A100)
    • 800 MHz (A110)

Celeron M

• Banias-512 0.13 µm process technology
  • Introduced March 2003
  • 64 KB L1 cache
  • 512 KB L2 cache (integrated)
  • SSE2 SIMD instructions
  • No SpeedStep technology, is not part of the 'Centrino' package
  • Family 6 model 9
  • Variants
    • 310 – 1.20 GHz
    • 320 – 1.30 GHz
    • 330 – 1.40 GHz
    • 340 – 1.50 GHz
• Dothan-1024 90 nm process technology
  • 64 KB L1 cache
  • 1 MB L2 cache (integrated)
  • SSE2 SIMD instructions
  • No SpeedStep technology, is not part of the 'Centrino' package
  • Variants
    • 350 – 1.30 GHz
    • 350J – 1.30 GHz, with Execute Disable bit
    • 360 – 1.40 GHz
    • 360J – 1.40 GHz, with Execute Disable bit
    • 370 – 1.50 GHz, with Execute Disable bit
      • Family 6, Model 13, Stepping 8
    • 380 – 1.60 GHz, with Execute Disable bit
    • 390 – 1.70 GHz, with Execute Disable bit
• Yonah-1024 65 nm process technology
  • 64 KB L1 cache
  • 1 MB L2 cache (integrated)
  • SSE3 SIMD instructions, 533 MHz front-side bus, execute-disable bit
  • No SpeedStep technology, is not part of the 'Centrino' package
  • Variants
    • 410 – 1.46 GHz
    • 420 – 1.60 GHz,
    • 423 – 1.06 GHz (ultra low voltage)
    • 430 – 1.73 GHz
    • 440 – 1.86 GHz
    • 443 – 1.20 GHz (ultra low voltage)
    • 450 – 2.00 GHz

Intel Core

In 2005, Intel improved its Pentium 4 twice. First, with the Prescott-2M, and then with Smithfield. The former was a 64-bit processor, based on the Prescott design, and the latter was a dual-core processor. They are fairly similar and have the same problems as other Pentium 4s: low instructions per cycle (IPC) throughput and difficulty in increasing the clock frequency due to current losses. These two processors, intended to limit losses while awaiting the Core 2 Duo, are not among Intel’s most highly regarded. And while the Pentium D (the commercial name of the Smithfield) does have two cores, in reality it’s an assembly of two Prescott dies in the same package.

• Yonah 0.065 µm (65 nm) process technology
  • Introduced January 2006
  • 533/667 MHz front side bus
  • 2 MB (Shared on Duo) L2 cache
  • SSE3 SIMD instructions
  • 31W TDP (T versions)
  • Family 6, Model 14
  • Variants:
    • Intel Core Duo T2700 2.33 GHz
    • Intel Core Duo T2600 2.16 GHz
    • Intel Core Duo T2500 2 GHz
    • Intel Core Duo T2450 2 GHz
    • Intel Core Duo T2400 1.83 GHz
    • Intel Core Duo T2300 1.66 GHz
    • Intel Core Duo T2050 1.6 GHz
    • Intel Core Duo T2300e 1.66 GHz
    • Intel Core Duo T2080 1.73 GHz
    • Intel Core Duo L2500 1.83 GHz (low voltage, 15W TDP)
    • Intel Core Duo L2400 1.66 GHz (low voltage, 15W TDP)
    • Intel Core Duo L2300 1.5 GHz (low voltage, 15W TDP)
    • Intel Core Duo U2500 1.2 GHz (ultra low voltage, 9W TDP)
    • Intel Core Solo T1350 1.86 GHz (533 FSB)
    • Intel Core Solo T1300 1.66 GHz
    • Intel Core Solo T1200 1.5 GHz

Dual-Core Xeon LV

• Sossaman 0.065 µm (65 nm) process technology
  • Introduced March 2006
  • Based on Yonah core, with SSE3 SIMD instructions
  • 667 MHz frontside bus
  • 2 MB Shared L2 cache
  • Variants
    • 2.0 GHz

32-bit processors: NetBurst microarchitecture

Pentium 4

• 0.18 µm process technology (1.40 and 1.50 GHz)
  • Introduced November 20, 2000
  • L2 cache was 256 KB Advanced Transfer Cache (Integrated)
  • Processor Package Style was PGA423, PGA478
  • System Bus clock rate 400 MHz
  • SSE2 SIMD Extensions
  • Number of Transistors 42 million
  • Used in desktops and entry-level workstations
• 0.18 µm process technology (1.7 GHz)
  • Introduced April 23, 2001
  • See the 1.4 and 1.5 chips for details
• 0.18 µm process technology (1.6 and 1.8 GHz)
  • Introduced July 2, 2001
  • See 1.4 and 1.5 chips for details
  • Core Voltage is 1.15 volts in Maximum Performance Mode; 1.05 volts in Battery Optimized Mode
  • Power <1 watt in Battery Optimized Mode
  • Used in full-size and then light mobile PCs
• 0.18 µm process technology Willamette (1.9 and 2.0 GHz)
  • Introduced August 27, 2001
  • See 1.4 and 1.5 chips for details
• Family 15 model 1
• Pentium 4 (2 GHz, 2.20 GHz)
  • Introduced January 7, 2002
• Pentium 4 (2.4 GHz)
  • Introduced April 2, 2002
• 0.13 µm process technology Northwood A (1.7, 1.8, 1.9, 2, 2.2, 2.4, 2.5, 2.6, 2.8(OEM),3.0(OEM) GHz)
  • Improved branch prediction and other microcodes tweaks
  • 512 KB integrated L2 cache
  • Number of transistors 55 million
  • 400 MHz system bus.
• Family 15 model 2
• 0.13 µm process technology Northwood B (2.26, 2.4, 2.53, 2.66, 2.8, 3.06 GHz)
  • 533 MHz system bus. (3.06 includes Intel's Hyper-Threading technology).
• 0.13 µm process technology Northwood C (2.4, 2.6, 2.8, 3.0, 3.2, 3.4 GHz)
  • 800 MHz system bus (all versions include Hyper-Threading)
  • 6500 to 10000 MIPS

Itanium (chronological entry)

• Introduced 2001
• See main entry

Xeon

• Official designation now Xeon, i.e. not "Pentium 4 Xeon"
• Xeon 1.4, 1.5, 1.7 GHz
  • Introduced May 21, 2001
  • L2 cache was 256 KB Advanced Transfer Cache (Integrated)
  • Processor Package Style was Organic Land Grid Array 603 (OLGA 603)
  • System Bus clock rate 400 MHz
  • SSE2 SIMD Extensions
  • Used in high-performance and mid-range dual processor enabled workstations
• Xeon 2.0 GHz and up to 3.6 GHz
  • Introduced September 25, 2001

Itanium 2 (chronological entry)

• Introduced July 2002
• See main entry

Mobile Pentium 4-M

• 0.13 µm process technology
• 55 million transistors
• cache L2 512 KB
• BUS a 400 MHz
• Supports up to 1 GB of DDR 266 MHz Memory
• Supports ACPI 2.0 and APM 1.2 System Power Management
• 1.3 V – 1.2 V (SpeedStep)
• Power: 1.2 GHz 20.8 W, 1.6 GHz 30 W, 2.6 GHz 35 W
• Sleep Power 5 W (1.2 V)
• Deeper Sleep Power = 2.9 W (1.0 V)

• • 1.40 GHz – 23 April 2002
  • 1.50 GHz – 23 April 2002
  • 1.60 GHz – 4 March 2002
  • 1.70 GHz – 4 March 2002
  • 1.80 GHz – 23 April 2002
  • 1.90 GHz – 24 June 2002
  • 2.00 GHz – 24 June 2002
  • 2.20 GHz – 16 September 2002
  • 2.40 GHz – 14 January 2003
  • 2.50 GHz – 16 April 2003
  • 2.60 GHz – 11 June 2003

Pentium 4 EE

• Introduced September 2003
• EE = "Extreme Edition"
• Built from the Xeon's "Gallatin" core, but with 2 MB cache

Pentium 4E

• Introduced February 2004
• built on 0.09 µm (90 nm) process technology Prescott (2.4A, 2.8, 2.8A, 3.0, 3.2, 3.4, 3.6, 3.8) 1 MB L2 cache
• 533 MHz system bus (2.4A and 2.8A only)
• Number of Transistors 125 million on 1 MB Models
• Number of Transistors 169 million on 2 MB Models
• 800 MHz system bus (all other models)
• Hyper-Threading support is only available on CPUs using the 800 MHz system bus.
• The processor's integer instruction pipeline has been increased from 20 stages to 31 stages, which theoretically allows for even greater bandwidth.
• 7500 to 11000 MIPS
• LGA 775 versions are in the 5xx series (32-bit) and 5x1 series (with Intel 64)
• The 6xx series has 2 MB L2 cache and Intel 64

Pentium 4F

• Introduced Spring 2004
• same core as 4E, "Prescott"
• 3.2–3.6 GHz
• starting with the D0 stepping of this processor, Intel 64 64-bit extensions has also been incorporated

64-bit processors: IA-64

• New instruction set, not at all related to x86.
• Before the feature was eliminated (Montecito, July 2006) IA-64 processors supported 32-bit x86 in hardware, but slowly (see its 2001 market reception and 2006 architectural ).

Itanium

• Code name Merced
• Family 7
• Released May 29, 2001
• 733 MHz and 800 MHz
• 2MB cache
• All recalled and replaced by Itanium-II

Itanium 2

• Family 0x1F
• Released July 2002
• 900 MHz – 1.6 GHz
• McKinley 900 MHz 1.5MB cache, Model 0x0
• McKinley 1 GHz, 3MB cache, Model 0x0
• Deerfield 1 GHz, 1.5MB cache, Model 0x1
• Madison 1.3 GHz, 3MB cache, Model 0x1
• Madison 1.4 GHz, 4MB cache, Model 0x1
• Madison 1.5 GHz, 6MB cache, Model 0x1
• Madison 1.67 GHz, 9MB cache, Model 0x1
• Hondo 1.4 GHz, 4MB cache, dual core MCM, Model 0x1

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