The 80486DX or, just 486, is emblematic of a certain
generation who were first discovering computers. In fact,
the very famous 486 DX2/66 was long considered the minimum
configuration for gamers. This processor
ushered in several interesting new features, like an on-chip FPU, data cache, and the first clock multiplier. The former
consisted of an x87 coprocessor built into the 486 DX (not
SX) series. An 8 KB Level 1 cache was built into the
processor (write-through type, then write-back with slightly
better performance). There was also the possibility of a
Level 2 cache on the motherboard (at the bus frequency).
The second generation of 486s had a CPU
multiplier, since the processor operated faster than the FSB,
with DX2 (2x multiplier) and DX4 (3x multiplier) versions.
Another anecdote: the “487SX” sold as an FPU for the 486SX
was actually a full 486DX that disabled and took the place
of the first processor.
Introduced April 10, 1989
Clock rates:
25 MHz with 20 MIPS (16.8 SPECint92, 7.40
SPECfp92)
33 MHz with 27 MIPS (22.4 SPECint92 on Micronics
M4P 128 KB L2), introduced May 7, 1990
50 MHz with 41 MIPS (33.4 SPECint92, 14.5
SPECfp92 on Compaq/50L 256 KB L2), introduced June
24, 1991
Bus Width 32 bits
Number of Transistors 1.2 million at 1 µm; the
50 MHz was at 0.8 µm
Addressable memory 4 GB
Virtual memory 1 TB
Level 1 cache of 8 KB on chip
Math coprocessor on chip
50X performance of the 8088
Used in Desktop computing and servers
Family 4 model 3
80486SX
Introduced April 22, 1991
Clock rates:
16 MHz with 13 MIPS
20 MHz with 16.5 MIPS, introduced September 16,
1991
25 MHz with 20 MIPS (12 SPECint92), introduced
September 16, 1991
33 MHz with 27 MIPS (15.86 SPECint92),
introduced September 21, 1992
Bus Width 32 bits
Number of Transistors 1.185 million at 1 µm and
900,000 at 0.8 µm
Addressable memory 4 GB
Virtual memory 1 TB
Identical in design to 486DX but without math
coprocessor. The first version was an 80486DX with
disabled math coprocessor in the chip and different pin
configuration. If the user needed math coprocessor
capabilities, he must add 487SX which was actually an
486DX with different pin configuration to prevent the
user from installing a 486DX instead of 487SX, so with
this configuration 486SX+487SX you had 2 identical CPU's
with only 1 effectively turned on
Used in low-cost entry to 486 CPU desktop computing,
as well as extensively used in low cost mobile
computing.
Upgradable with the
Intel OverDrive processor
Family 4 model 2
80486DX2
Introduced March 3, 1992
Runs at twice the speed of the external bus (FSB).
Clock rates:
40 MHz
50 MHz
66 MHz
100 MHz (this was only made for a short time due
to high failure rates)
80486SL
Introduced November 9, 1992
Clock rates:
20 MHz with 15.4MIPS
25 MHz with 19 MIPS
33 MHz with 25 MIPS
Bus Width 32 bits
Number of Transistors 1.4 million at 0.8 µm
Addressable memory 4 GB
Virtual memory 1 TB
Used in notebook computers
Family 4 model 3
80486DX4
Introduced March 7, 1994
Clock rates:
75 MHz with 53 MIPS (41.3 SPECint92, 20.1
SPECfp92 on Micronics M4P 256 KB L2)
100 MHz with 70.7 MIPS (54.59 SPECint92, 26.91
SPECfp92 on Micronics M4P 256 KB L2)
Number of Transistors 1.6 million at 0.6 µm
Bus width 32 bits
Addressable memory 4 GB
Virtual memory 64 TB
Pin count 168
PGA Package, 208
sq ftP Package
Used in high performance entry-level desktops and
value notebooks
Family 4 model 8
32-bit processors:
P5 microarchitecture
Original
Pentium
The Pentium, so named because Intel wasn’t
allowed to trademark a name made up of numbers only so Intel
drop the traditional model number, was famous because of a
bug it contained. On the first generations of Pentiums,
certain division operations produced an incorrect result.
Intel replaced the processors, but the damage was done. A
very rare error gave rise to the first big IT media buzz.
The Pentium was sold in three different
versions, the first without a CPU multiplier, the second
with a multiplier (including the very familiar Pentium 166),
and the last with the SIMD instruction set for x86s, MMX.
The Pentium MMX also increased the size of the Level 1 cache
and brought in a few minor improvements. This was the first
Intel x86 capable of executing two instructions in parallel.
The L2 cache was on the motherboard with these processors
(running at the frequency of the FSB).
Bus width 64 bits
System bus clock rate 60 or 66 MHz
Address bus 32 bits
Addressable Memory 4 GB
Virtual Memory 64 TB
Superscalar architecture
Runs on 5 volts
Used in desktops
8 KB of instruction
cache
8 KB of data cache
P5 –
0.8 µm process technology
Introduced March 22, 1993
Number of transistors 3.1 million
Socket 4 273 pin PGA processor package
Package dimensions 2.16" × 2.16"
Family 5 model 1
Variants
60 MHz with 100 MIPS (70.4 SPECint92, 55.1
SPECfp92 on Xpress 256 KB L2)
66 MHz with 112 MIPS (77.9 SPECint92, 63.6
SPECfp92 on Xpress 256 KB L2)
P54 –
0.6 µm process technology
Socket 5 296/320 pin PGA package
Number of transistors 3.2 million
Variants
75 MHz with 126.5 MIPS (2.31 SPECint95, 2.02
SPECfp95 on Gateway P5 256K L2)
Introduced October 10, 1994
90, 100 MHz with 149.8 and 166.3 MIPS respectively
(2.74 SPECint95, 2.39 SPECfp95 on Gateway P5 256K L2 and
3.30 SPECint95, 2.59 SPECfp95 on Xpress 1ML2
respectively)
Introduced March 7, 1994
P54CQS –
0.35 µm process technology
Socket 5 296/320 pin PGA package
Number of transistors 3.2 million
Variants
120 MHz with 203 MIPS (3.72 SPECint95, 2.81
SPECfp95 on Xpress 1MB L2)
Introduced March 27, 1995
P54CS –
0.35 µm process technology
Number of transistors 3.3 million
90 mm˛ die size
Family 5 model 2
Variants
Socket 5 296/320 pin PGA package
133 MHz with 218.9 MIPS (4.14 SPECint95,
3.12 SPECfp95 on Xpress 1MB L2)
Introduced June 12, 1995
150, 166 MHz with 230 and 247 MIPS
respectively
Introduced January 4, 1996
Socket 7 296/321 pin PGA package
200 MHz with 270 MIPS (5.47 SPECint95, 3.68
SPECfp95)
Introduced June 10, 1996
Pentium with MMX Technology
P55C –
0.35 µm process technology
Introduced January 8, 1997
Intel
MMX (instruction set) support
Socket 7 296/321 pin PGA (pin grid array)
package
16 KB L1 instruction cache
16 KB L1 data cache
Number of transistors 4.5 million
System bus clock rate 66 MHz
Basic P55C is family 5 model 4, mobile are
family 5 model 7 and 8
Variants
166, 200 MHz Introduced January 8, 1997
233 MHz Introduced June 2, 1997
133 MHz (Mobile)
166, 266 MHz (Mobile) Introduced January 12,
1998
200, 233 MHz (Mobile) Introduced September
8, 1997
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