32-bit processors: P6/Pentium M microarchitecture

Pentium Pro

The Pentium Pro was the first x86 CPU able to manage more than 4 GB of RAM using Physical Address Extension (PAE), 36-bit address size, and thus 64 GB. An interesting point is that this processor was also the first P6 (the architecture the Core 2 processors are loosely derived from) and also the first x86 to include a Level 2 cache on the processor instead of on the motherboard. In fact, between 256 KB and 1 MB of cache were placed next to the CPU, on the same socket, making the L2 cache on-package as opposed to on-chip, clocked at the same frequency as the CPU.

This processor also had a bit of a performance issue. It ran great in 32-bit applications, but was much slower with software still written in 16 bits (like Windows 95). The cause was simple: access to 16-bit registers caused problems with management of the (32-bit) registers, which canceled out the advantages of the Pentium Pro’s out-of-order architecture.

• Introduced November 1, 1995
• Precursor to Pentium II and IIII
• Primarily used in server systems
• Socket 8 processor package (387 pins) (Dual SPGA)
• Number of transistors 5.5 million
• Family 6 model 1
• 0.6 µm process technology
  • 16 KB L1 cache
  • 256 KB integrated L2 cache
  • 60 MHz system bus clock rate
  • Variants
    • 150 MHz
• 0.35 µm process technology, or 0.35 µm CPU with 0.6 µm L2 cache
  • Number of transistors 5.5 million
  • 512 KB or 256 KB integrated L2 cache
  • 60 or 66 MHz system bus clock rate
  • Variants
    • 166 MHz (66 MHz bus clock rate, 512 KB 0.35 µm cache) Introduced November 1, 1995
    • 180 MHz (60 MHz bus clock rate, 256 KB 0.6 µm cache) Introduced November 1, 1995
    • 200 MHz (66 MHz bus clock rate, 256 KB 0.6 µm cache) Introduced November 1, 1995
    • 200 MHz (66 MHz bus clock rate, 512 KB 0.35 µm cache) Introduced November 1, 1995
    • 200 MHz (66 MHz bus clock rate, 1 MB 0.35 µm cache) Introduced August 18, 1997

Pentium II

The Pentium II was an adaptation of the Pentium Pro aimed at the general public. It was quite similar to the Pentium Pro, but the cache memory was different. Instead of using a cache at the same frequency as the processor (which is expensive), the 512 KB Level 2 cache operated at half-frequency. In addition, the Pentium II abandoned the classic socket for a cartridge containing the processor and the Level 2 cache, which was in the cartridge and not on the motherboard or in the processor itself.

New features compared to the Pentium Pro were essentially MMX (SIMD) support and a doubling of the Level 1 cache. The first Pentium III (Katmai) was very similar to the Pentium II. Released in 1999, its new feature was essentially support for SSE (SIMD instructions), but the rest was identical.

• Introduced May 7, 1997
• Pentium Pro with MMX and improved 16-bit performance
• 242-pin Slot 1 (SEC) processor package
• Slot 1
• Number of transistors 7.5 million
• 32 KB L1 cache
• 512 KB ½ bandwidth external L2 cache
• The only Pentium II that did not have the L2 cache at ½ bandwidth of the core was the Pentium II 450 PE.
• Klamath – 0.35 µm process technology (233, 266, 300 MHz)
  • 66 MHz system bus clock rate
  • Family 6 model 3
  • Variants
    • 233, 266, 300 MHz Introduced May 7, 1997
• Deschutes – 0.25 µm process technology (333, 350, 400, 450 MHz)
  • Introduced January 26, 1998
  • 66 MHz system bus clock rate (333 MHz variant), 100 MHz system bus clock rate for all models after
  • Family 6 model 5
  • Variants
    • 333 MHz Introduced January 26, 1998
    • 350, 400 MHz Introduced April 15, 1998
    • 450 MHz Introduced August 24, 1998
    • 233, 266 MHz (Mobile) Introduced April 2, 1998
    • 333 MHz Pentium II Overdrive processor for Socket 8 Introduced August 10, 1998;
    • 300 MHz (Mobile) Introduced September 9, 1998
    • 333 MHz (Mobile)

Celeron (Pentium II-based)

At the end of the 1990s, Intel launched two of its best-known processor brands: Celeron and Xeon. The former was aimed at the budget market and the latter at servers, and sometimes workstations. The first Celeron (Covington) was a Pentium II without a Level 2 cache, and suffered extremely poor performance, whereas the Pentium II Xeon had a large cache. Even now, both brands still exist—Celeron for the entry-level market (generally with a reduced cache and a slower FSB) and Xeon for servers (with a fast FSB, sometimes more cache, and high clock speeds).

Intel quickly added a cache to the Celeron with the Mendocino model (128 KB). The Celeron 300A is famous for its overclocking capacities, able to go 50% or more above its rated clock speed much of the time.

• Covington – 0.25 µm process technology
  • Introduced April 15, 1998
  • 242-pin Slot 1 SEPP (Single Edge Processor Package)
  • Number of transistors 7.5 million
  • 66 MHz system bus clock rate
  • Slot 1
  • 32 KB L1 cache
  • No L2 cache
  • Variants
    • 266 MHz Introduced April 15, 1998
    • 300 MHz Introduced June 9, 1998
• Mendocino – 0.25 µm process technology
  • Introduced August 24, 1998
  • 242-pin Slot 1 SEPP (Single Edge Processor Package), Socket 370 PPGA package
  • Number of transistors 19 million
  • 66 MHz system bus clock rate
  • Slot 1, Socket 370
  • 32 KB L1 cache
  • 128 KB integrated cache
  • Family 6 model 6
  • Variants
    • 300, 333 MHz Introduced August 24, 1998
    • 366, 400 MHz Introduced January 4, 1999
    • 433 MHz Introduced March 22, 1999
    • 466 MHz
    • 500 MHz Introduced August 2, 1999
    • 533 MHz Introduced January 4, 2000
    • 266 MHz (Mobile)
    • 300 MHz (Mobile)
    • 333 MHz (Mobile) Introduced April 5, 1999
    • 366 MHz (Mobile)
    • 400 MHz (Mobile)
    • 433 MHz (Mobile)
    • 450 MHz (Mobile) Introduced February 14, 2000
    • 466 MHz (Mobile)
    • 500 MHz (Mobile) Introduced February 14, 2000

Pentium II Xeon (chronological entry)

• Introduced June 29, 1998

Pentium III

• Katmai – 0.25 µm process technology
  • Introduced February 26, 1999
  • Improved PII, i.e. P6-based core, now including Streaming SIMD Extensions (SSE)
  • Number of transistors 9.5 million
  • 512 KB ½ bandwidth L2 External cache
  • 242-pin Slot 1 SECC2 (Single Edge Contact cartridge 2) processor package
  • System Bus clock rate 100 MHz, 133 MHz (B-models)
  • Slot 1
  • Family 6 model 7
  • Variants
    • 450, 500 MHz Introduced February 26, 1999
    • 550 MHz Introduced May 17, 1999
    • 600 MHz Introduced August 2, 1999
    • 533, 600 MHz Introduced (133 MHz bus clock rate) September 27, 1999
• Coppermine – 0.18 µm process technology
  • Introduced October 25, 1999
  • Number of transistors 28.1 million
  • 256 KB Advanced Transfer L2 Cache (Integrated)
  • 242-pin Slot-1 SECC2 (Single Edge Contact cartridge 2) processor package, 370-pin FC-PGA (Flip-chip pin grid array) package
  • System Bus clock rate 100 MHz (E-models), 133 MHz (EB models)
  • Slot 1, Socket 370
  • Family 6 model 8
  • Variants
    • 500 MHz (100 MHz bus clock rate)
    • 533 MHz
    • 550 MHz (100 MHz bus clock rate)
    • 600 MHz
    • 600 MHz (100 MHz bus clock rate)
    • 650 MHz (100 MHz bus clock rate) Introduced October 25, 1999
    • 667 MHz Introduced October 25, 1999
    • 700 MHz (100 MHz bus clock rate) Introduced October 25, 1999
    • 733 MHz Introduced October 25, 1999
    • 750, 800 MHz (100 MHz bus clock rate) Introduced December 20, 1999
    • 850 MHz (100 MHz bus clock rate) Introduced March 20, 2000
    • 866 MHz Introduced March 20, 2000
    • 933 MHz Introduced May 24, 2000
    • 1000 MHz Introduced March 8, 2000 (not widely available at time of release)
    • 1100 MHz
    • 1133 MHz (first version recalled, later re-released)
    • 400, 450, 500 MHz (Mobile) Introduced October 25, 1999
    • 600, 650 MHz (Mobile) Introduced January 18, 2000
    • 700 MHz (Mobile) Introduced April 24, 2000
    • 750 MHz (Mobile) Introduced June 19, 2000
    • 800, 850 MHz (Mobile) Introduced September 25, 2000
    • 900, 1000 MHz (Mobile) Introduced March 19, 2001
• Tualatin – 0.13 µm process technology
  • Introduced July 2001
  • Number of transistors 28.1 million
  • 32 KB L1 cache
  • 256 KB or 512 KB Advanced Transfer L2 cache (integrated)
  • 370-pin FC-PGA2 (flip-chip pin grid array) package
  • 133 MHz system bus clock rate
  • Socket 370
  • Family 6 model 11
  • Variants
    • 1133 MHz (256 KB L2)
    • 1133 MHz (512 KB L2)
    • 1200 MHz
    • 1266 MHz (512 KB L2)
    • 1333 MHz
    • 1400 MHz (512 KB L2)

Intel processors page 4 >

Back to the Computer Architecture Page <